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FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
14 years 4 months ago
Design of FPGA interconnect for multilevel metalization
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
Raphael Rubin, André DeHon
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 4 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
14 years 4 months ago
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
—As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put diï¬...
Chien-Chang Chen, Wai-Kei Mak
MTDT
2006
IEEE
101views Hardware» more  MTDT 2006»
14 years 4 months ago
FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment
We present a ROM compiler programmable from via 1 to via n – 2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. Wit...
Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-M...