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MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
13 years 10 months ago
Wrong-path Instruction Prefetching
Jim Pierce, Trevor N. Mudge
MICRO
1996
IEEE
142views Hardware» more  MICRO 1996»
13 years 10 months ago
Compiler Synthesized Dynamic Branch Prediction
Branch prediction is the predominant approach for minimizing the pipeline breaks caused by branch instructions. Traditionally, branch prediction is accomplished in one of two ways...
Scott A. Mahlke, Balas K. Natarajan
MICRO
1996
IEEE
81views Hardware» more  MICRO 1996»
13 years 10 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
Eric Schnarr, James R. Larus
MICRO
1996
IEEE
89views Hardware» more  MICRO 1996»
13 years 10 months ago
The Performance Potential of Data Dependence Speculation & Collapsing
Yiannakis Sazeides, Stamatis Vassiliadis, James E....
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 10 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
13 years 10 months ago
Exceeding the Dataflow Limit via Value Prediction
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
Mikko H. Lipasti, John Paul Shen
MICRO
1996
IEEE
97views Hardware» more  MICRO 1996»
13 years 10 months ago
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs
Much of the previous work on modulo scheduling has targeted numeric programs, in which, often, the majority of the loops are well-behaved loop-counter-based loops without early ex...
Daniel M. Lavery, Wen-mei W. Hwu
MICRO
1996
IEEE
173views Hardware» more  MICRO 1996»
13 years 10 months ago
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
The Java bytecode language is emerging as a software distribution standard. With major vendors committed to porting the Java run-time environment to their platforms, programs in J...
Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei ...
MICRO
1996
IEEE
106views Hardware» more  MICRO 1996»
13 years 10 months ago
Optimization of Machine Descriptions for Efficient Use
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...
John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna...
MICRO
1996
IEEE
89views Hardware» more  MICRO 1996»
13 years 10 months ago
Custom-fit Processors: Letting Applications Define Architectures
Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desol...