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95
Voted
PATMOS
2005
Springer
84
views
Modeling and Simulation
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PATMOS 2005
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Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
15 years 8 months ago
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www.ics.forth.gr
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
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90
Voted
VLSID
2001
IEEE
98
views
VLSI
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VLSID 2001
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Complexity Of Minimum-Delay Gate Resizing
16 years 3 months ago
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www.eecs.umich.edu
Supratik Chakraborty, Rajeev Murgai
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