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ISPD
1999
ACM
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ISPD 1999
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A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
15 years 7 months ago
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www.cs.york.ac.uk
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
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