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CODES
2010
IEEE
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Dynamic, non-linear cache architecture for power-sensitive mobile processors
12 years 7 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
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Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
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