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133
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ATS
2005
IEEE
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ATS 2005
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Untestable Multi-Cycle Path Delay Faults in Industrial Designs
15 years 9 months ago
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www.cesca.centers.vt.edu
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
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