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ISCAS
2007
IEEE

139views Hardware» more ISCAS 2007»

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

15 years 9 months ago

Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...

Yang Sun, Marjan Karkooti, Joseph R. Cavallaro

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