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IPPS
2010
IEEE
13 years 10 months ago
Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance
Increasing the core-count on current and future processors is posing critical challenges to the memory subsystem to efficiently handle concurrent memory requests. The current tren...
José Carlos Sancho, Michael Lang 0003, Darr...
RTAS
2010
IEEE
13 years 10 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
FPL
2009
Springer
132views Hardware» more  FPL 2009»
14 years 4 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
IPPS
2002
IEEE
14 years 5 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha