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133
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VLSID
2002
IEEE
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VLSI
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VLSID 2002
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A Heuristic for Clock Selection in High-Level Synthesis
16 years 3 months ago
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www.ece.lsu.edu
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
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