Sciweavers

ETS
2011
IEEE
212views Hardware» more  ETS 2011»
12 years 5 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
CAL
2008
13 years 5 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
13 years 11 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
CODES
2005
IEEE
13 years 11 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...
NOCS
2009
IEEE
14 years 5 days ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...