Sciweavers

    FPGA
    1995
    ACM
    105views FPGA» more  FPGA 1995»
    On Nominal Delay Minimization in LUT-based FPGA Technology Mapping
    15 years 6 months ago
    On Nominal Delay Minimization in LUT-based FPGA Technology Mapping
    Download  cadlab.cs.ucla.edu
    We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-opt...
    Jason Cong, Yuzheng Ding
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    i2PDF i2Img i2Text i2OCR i2Symbol i2Type i2Speak i2Style i2Arabic i2Bopomo Latex Equation Editor
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2026, USA.