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ISLPED
2010
ACM
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ISLPED 2010
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An energy efficient cache design using spin torque transfer (STT) RAM
15 years 3 months ago
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www.ece.gatech.edu
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
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