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136
Voted
VLSID
2006
IEEE
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VLSID 2006
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Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
16 years 3 months ago
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www.cse.unt.edu
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
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