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VLSID
2002
IEEE
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VLSI
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VLSID 2002
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A Power Minimization Technique for Arithmetic Circuits by Cell Selection
16 years 3 months ago
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www.c.csce.kyushu-u.ac.jp
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, ...
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