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DFT
2003
IEEE
117views VLSI» more  DFT 2003»
15 years 4 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
102
Voted
DCC
2007
IEEE
15 years 10 months ago
Small weight codewords in LDPC codes defined by (dual) classical generalized quadrangles
We find lower bounds on the minimum distance and characterize codewords of small weight in low-density parity check codes defined by (dual) classical generalized quadrangles. We a...
Jon-Lark Kim, Keith E. Mellinger, Leo Storme
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
15 years 11 months ago
Implementing LDPC Decoding on Network-on-Chip
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...