64
Voted
PATMOS
2005
Springer
15 years 6 months ago
2005
Springer
73
Voted
PATMOS
2005
Springer
15 years 6 months ago
2005
Springer
A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as ...
83
Voted
PATMOS
2005
Springer
15 years 6 months ago
2005
Springer
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...