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105
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ISQED
2010
IEEE
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ISQED 2010
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Assessing chip-level impact of double patterning lithography
15 years 9 months ago
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vlsicad.ucsd.edu
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
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