Sciweavers

HIPC
2009
Springer
13 years 5 months ago
Three scalable approaches to improving many-core throughput for a given peak power budget
Recently proposed techniques for peak power management [18] involve centralized decisionmaking and assume quick evaluation of the various power management states. These techniques...
John Sartori, Rakesh Kumar
ETS
2009
IEEE
99views Hardware» more  ETS 2009»
13 years 5 months ago
On Minimization of Peak Power for Scan Circuit during Test
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...
TC
2008
13 years 7 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
FPL
2008
Springer
91views Hardware» more  FPL 2008»
13 years 9 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 9 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
13 years 11 months ago
K2: an estimator for peak sustainable power of VLSI circuits
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
DAC
2004
ACM
13 years 11 months ago
On test generation for transition faults with minimized peak power dissipation
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
Wei Li, Sudhakar M. Reddy, Irith Pomeranz
DATE
1999
IEEE
118views Hardware» more  DATE 1999»
13 years 11 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
13 years 12 months ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
VTS
2002
IEEE
109views Hardware» more  VTS 2002»
14 years 11 days ago
Controlling Peak Power During Scan Testing
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
Ranganathan Sankaralingam, Nur A. Touba