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109
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EUC
2004
Springer
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Applied Computing
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EUC 2004
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Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints
15 years 6 months ago
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In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise ...
Chantana Chantrapornchai, Wanlop Surakumpolthorn, ...
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