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95
Voted
DDECS
2009
IEEE
111
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Hardware
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DDECS 2009
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0.5V 160-MHz 260uW all digital phase-locked loop
15 years 9 months ago
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www.ncu.edu.tw
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hs...
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