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104
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VTS
2005
IEEE
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VTS 2005
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Synthesis of Low Power CED Circuits Based on Parity Codes
15 years 8 months ago
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An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
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