102
click to vote
DSN
2011
IEEE
13 years 9 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
TC
1998
14 years 9 months ago
1998
—When parallel programs are executed on multiprocessors with private caches, a set of data may be repeatedly used and modified by different threads. Such data sharing can often r...
75
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...