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172
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EVOW
1999
Springer
111
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Artificial Intelligence
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EVOW 1999
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Test Pattern Generation Under Low Power Constraints
15 years 7 months ago
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www.cad.polito.it
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
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