Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
Chaitin proved that register allocation is equivalent to graph coloring and hence NP-complete. Recently, Bouchez, Brisk, and Hack have proved independently that the interference gr...
Commonly-used memory units enable a processor to load and store multiple registers in one instruction. We showed in 2003 how to extend gcc with a stack-location-allocation (SLA) ph...
As register allocation is one of the most important phases in optimizing compilers, much work has been done to improve its quality and speed. We present a novel register allocation...
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...
Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Kare...
Abstract. Fast dynamic compilers trade code quality for short compilation time in order to balance application performance and startup time. This paper investigates the interplay o...
A linear-scan algorithm directs the global allocation of register candidates to registers based on a simple linear sweep over the program being compiled. This approach to register...
This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP registe...
An approach of doing register allocation beyond basic blocks for low energy is presented in this paper. With careful analysis of boundary conditions between consecutive blocks, ou...