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ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 10 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba