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124
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ICCAD
2003
IEEE
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ICCAD 2003
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Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
15 years 11 months ago
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vlsicad.ucsd.edu
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...
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