Sciweavers

DFT
2005
IEEE
132views VLSI» more  DFT 2005»
14 years 4 days ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba