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ASYNC
2000
IEEE
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ASYNC 2000
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An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
15 years 7 months ago
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www.cl.cam.ac.uk
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
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