Sciweavers

GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
15 years 2 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
54
Voted
ISQED
2008
IEEE
109views Hardware» more  ISQED 2008»
15 years 3 months ago
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation
This paper examines latch style voltage mode sense amplifiers for operation in the sub-threshold region, where VDD<VT. We show that the offset gets worse relative to strong inv...
Joseph F. Ryan, Benton H. Calhoun