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117
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DAC
1994
ACM
106
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Computer Architecture
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DAC 1994
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Clock Grouping: A Low Cost DFT Methodology for Delay Testing
15 years 7 months ago
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www.cs.york.ac.uk
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
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