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119
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EURODAC
1995
IEEE
126
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VHDL
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EURODAC 1995
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Use of embedded scheduling to compile VHDL for effective parallel simulation
15 years 6 months ago
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www.cs.york.ac.uk
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
John Willis, Zhiyuan Li, Tsang-Puu Lin
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