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114
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ISQED
2006
IEEE
90
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Hardware
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ISQED 2006
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Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
15 years 8 months ago
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www.cse.psu.edu
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
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