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119
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VLSI
2005
Springer
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Software Engineering
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VLSI 2005
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Pareto Points in SRAM Design Using the Sleepy Stack Approach
15 years 9 months ago
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codesign.ece.gatech.edu
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
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