SRAM cell architecture

103

ISLPED
1996
ACM

103views Hardware» more ISLPED 1996»

A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving

15 years 7 months ago

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This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...

Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, ...

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