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ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 10 months ago
Statistical timing analysis with two-sided constraints
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
Khaled R. Heloue, Farid N. Najm
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 10 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 10 months ago
Guaranteeing performance yield in high-level synthesis
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
DAC
2005
ACM
15 years 2 months ago
Statistical static timing analysis: how simple can we get?
Chirayu S. Amin, Noel Menezes, Kip Killpack, Flore...
DAC
2004
ACM
15 years 2 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi