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108
Voted
GLVLSI
2009
IEEE
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VLSI
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GLVLSI 2009
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Buffer design and optimization for lut-based structured ASIC design styles
15 years 9 months ago
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nthucad.cs.nthu.edu.tw
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
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