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119
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VLSI
2005
Springer
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Software Engineering
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VLSI 2005
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Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
15 years 8 months ago
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www.are-ata.org
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
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