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DAC
2012
ACM
11 years 6 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
DT
2010
99views more  DT 2010»
13 years 4 months ago
CEDA Currents
specified at levels of abstraction higher than the Register Transfer Level (RTL) in hardware description. The essential feature of a behavioral description is that, the designer on...
ICCTA
2007
IEEE
13 years 8 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
LCTRTS
1999
Springer
13 years 8 months ago
A Software Synthesis Tool for Distributed Embedded System Design
We present a design tool for automated synthesis of embedded systems on distributed COTS-based platforms. Our synthesis tool consists of (1) a graphical user interface for input o...
Dong-In Kang, Richard Gerber, Leana Golubchik, Jef...
FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
13 years 9 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
13 years 9 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
DATE
2003
IEEE
152views Hardware» more  DATE 2003»
13 years 9 months ago
Synthesis of CMOS Analog Cells Using AMIGO
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud...
ISLPED
2009
ACM
125views Hardware» more  ISLPED 2009»
13 years 11 months ago
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Jason Cong, Bin Liu, Zhiru Zhang