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105
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DATE
2010
IEEE
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DATE 2010
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Exploiting local logic structures to optimize multi-core SoC floorplanning
15 years 8 months ago
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Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
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