100
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EUROPAR
2011
Springer
13 years 12 months ago
2011
Springer
DOALL loops are tiled to exploit DOALL parallelism and data locality on GPUs. In contrast, due to loop-carried dependences, DOACROSS loops must be skewed first in order to make ti...
112
Voted
PCI
2005
Springer
15 years 5 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
81
Voted
CF
2006
ACM
15 years 6 months ago
2006
ACM
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...