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    TODAES
    1998
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    Optimal river routing with crosstalk constraints
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    Optimal river routing with crosstalk constraints
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    Hai Zhou, D. F. Wong
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    TODAES
    1998
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    The edge-based design rule model revisited
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    The edge-based design rule model revisited
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    Michael A. Riepe, Karem A. Sakallah
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    TODAES
    1998
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    Functional test generation for delay faults in combinational circuits
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    Functional test generation for delay faults in combinational circuits
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    Irith Pomeranz, Sudhakar M. Reddy
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    TODAES
    1998
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    Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
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    Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
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    Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
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    TODAES
    1998
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    Estimation of lower bounds in scheduling algorithms for high-level synthesis
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    Estimation of lower bounds in scheduling algorithms for high-level synthesis
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    Giri Tiruvuri, Moon Chung
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    TODAES
    1998
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    Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
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    Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
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    Dinesh P. Mehta
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    TODAES
    1998
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    Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems
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    Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems
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    C.-J. Richard Shi, Janusz A. Brzozowski
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    TODAES
    1998
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    A new viewpoint on code generation for directed acyclic graphs
    15 years 1 days ago
    A new viewpoint on code generation for directed acyclic graphs
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    Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, S...
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    TODAES
    1998
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    Breakpoints and breakpoint detection in source-level emulation
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    Breakpoints and breakpoint detection in source-level emulation
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    Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull
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    70
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    TODAES
    1998
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    Confidence analysis for defect-level estimation of VLSI random testing
    15 years 1 days ago
    Confidence analysis for defect-level estimation of VLSI random testing
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    Wen-Ben Jone, K. S. Tsai
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