Sciweavers

107
Voted
TVLSI
2002
93views more  TVLSI 2002»
15 years 19 hour ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
TVLSI
2002
130views more  TVLSI 2002»
15 years 19 hour ago
HW/SW codesign techniques for dynamically reconfigurable architectures
Abstract--Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. However, no previous work has been carried out ...
Juanjo Noguera, Rosa M. Badia
105
Voted
TVLSI
2002
102views more  TVLSI 2002»
15 years 19 hour ago
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
Ramesh Karri, Kaijie Wu
88
Voted
TVLSI
2002
102views more  TVLSI 2002»
15 years 19 hour ago
Power-optimal encoding for a DRAM address bus
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
Wei-Chung Cheng, Massoud Pedram
TVLSI
2002
102views more  TVLSI 2002»
15 years 19 hour ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
TVLSI
2002
91views more  TVLSI 2002»
15 years 19 hour ago
On the design of low-voltage, low-power CMOS analog multipliers for RF applications
Carl James Debono, Franco Maloberti, Joseph Micall...
97
Voted
TVLSI
2002
121views more  TVLSI 2002»
15 years 19 hour ago
On-chip decoupling capacitor optimization using architectural level prediction
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills