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109
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ICCAD
2005
IEEE
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ICCAD 2005
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Gate sizing using incremental parameterized statistical timing analysis
15 years 11 months ago
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vlsida.soe.ucsc.edu
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
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