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    FPL
    2008
    Springer
    129views Hardware» more  FPL 2008»
    Power reduction techniques for Dynamically Reconfigurable Processor Arrays
    14 years 10 months ago
    Power reduction techniques for Dynamically Reconfigurable Processor Arrays
    Download  www.am.ics.keio.ac.jp
    The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
    Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...
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