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96
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DAC
2005
ACM
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Computer Architecture
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DAC 2005
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Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
16 years 3 months ago
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eda.ee.ucla.edu
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
Yan Lin, Lei He
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