Sciweavers

    187
    Voted
    3DIC
    2009
    IEEE
    279views Hardware» more  3DIC 2009»
    Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
    15 years 10 months ago
    Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
    Download  www.ipack.kth.se
    Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
    Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    i2PDF i2Img i2Text i2OCR i2Symbol i2Type i2Speak i2Style i2Arabic i2Bopomo Latex Equation Editor
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2026, USA.