VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
This paper introduces a new numerical approximation technique, called the Differential Quadrature Method (DQM), in order to derive the rational ABCD matrix representing the high-s...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
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VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
- This work presents accurate closed-form expressions for the interconnect energy dissipation in high-speed ULSI circuits. Unlike previous works, the energy is calculated using an ...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...