Sciweavers

VTS
2003
IEEE
83views Hardware» more  VTS 2003»
14 years 3 months ago
SOC Test Scheduling Using Simulated Annealing
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Hua...
VTS
2003
IEEE
87views Hardware» more  VTS 2003»
14 years 3 months ago
Efficient Seed Utilization for Reseeding based Compression
Erik H. Volkerink, Subhasish Mitra
VTS
2003
IEEE
95views Hardware» more  VTS 2003»
14 years 3 months ago
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
VTS
2003
IEEE
131views Hardware» more  VTS 2003»
14 years 3 months ago
Efficient Implication - Based Untestable Bridge Fault Identifier
: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...
Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, ...
VTS
2003
IEEE
87views Hardware» more  VTS 2003»
14 years 3 months ago
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate con...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
14 years 3 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
VTS
2003
IEEE
88views Hardware» more  VTS 2003»
14 years 3 months ago
Use of Multiple IDDQ Test Metrics for Outlier Identification
With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for IDDQ test due to ...
Sagar S. Sabade, D. M. H. Walker
VTS
2003
IEEE
104views Hardware» more  VTS 2003»
14 years 3 months ago
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detectio...
Janak H. Patel, Steven S. Lumetta, Sudhakar M. Red...
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 3 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
14 years 3 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...