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SPIN
2004
Springer
13 years 11 months ago
Formal Analysis of Processor Timing Models
Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution
Reinhard Wilhelm
ECRTS
2005
IEEE
13 years 12 months ago
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Antonio Martí Campoy, Isabelle Puaut, Angel...
CODES
2007
IEEE
14 years 17 days ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling