Timing variation-aware high-level synthesis

—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the current timing variation-aware HLS techniques cannot support the following two critical factors at all: (i) non-Gaussian delay distribution of ‘module patterns’ used in scheduling and binding and (ii) correlation of timing variation between module patterns. However, without considering these factors, the synthesis results would be far less accurate in timing, being very likely to fail in timing closure. Even though there are advances in the logic level for SSTAs that support (i) and (ii), the manipulation and computation of (i) and (ii) in the course of scheduling and binding in HLS are unique in that there are no concepts of module sharing and performance yield computation in the logic level. Specifically, we propose a novel yield computation technique to handle the non-Gaussian timing variation of module pat...

• Type: Conference
• Year: 2007
• Where: ICCAD
• Authors: Jongyoon Jung, Taewhan Kim
• Keywords: Hardware, ICCAD 2007, Performance Yield Computation, Performance Yield Constraints, Yield Computation Technique